At present, a growing chorus of voices is clamoring for energy conservation in facilities and equipment in order to reduce costs and slow global warming. As technology to realize energy conservation, technology has been known that operates facilities and equipment by appropriately switching among a plurality of energy-saving modes. Among these energy-saving modes are, for example, a normal-frequency mode with relatively large energy consumption that operates under a normal clock frequency, and a low-frequency mode with smaller energy consumption than the normal-frequency mode that operates at a lower frequency than the normal clock frequency.
As this type of technology, Patent Literature 1 (Unexamined Japanese Patent Application KOKAI Publication No. 2004-242217) for example discloses a power consumption control device provided with a clock switch control circuit that measures a prescribed passage of time with a signal input from outside or a preset timing as the starting point and switches to a different power-saving mode at a prescribed time after the point in time when the prescribed passage of time has elapsed, and a PLL that switches the operating frequency in accordance with the switched energy-saving mode, in a power consumption control device that controls power consumption in accordance with any of a plurality of power consumption modes.
In addition, Patent Literature 2 (Unexamined Japanese Patent Application KOKAI Publication No. 2000-278104) and Patent Literature 3 (Unexamined Japanese Patent Application KOKAI Publication No. H08-23274) disclose technology for appropriately counting the pulse number of a standard frequency and the pulse number of a clock signal generated by a VCO (Voltage Controlled Oscillator) in order to detect with a PLL (Phase Locked Loop) that the frequency of the clock signal generated by the VCO matches or is higher or lower than a target frequency.
However, in the power consumption control device disclosed in Patent Literature 1, there are cases in which the operating frequency changes swiftly when switching operating frequencies because a format is adopted in which the frequency (operating frequency) of the clock signal generated by the PLL switches all at once to the target frequency. When the operating frequency changes rapidly in this manner, there are cases in which operation of the supply destination of the clock signal (the CPU (Central Processing Unit) and the like) becomes unstable (for example, software monitoring the operation of the PLL or the like becomes unstable, so the CPU and the like become unstable). On the other hand, it is desirable to change operating frequencies in a short time in order to respond to demand for faster processing when changing operating frequencies. This kind of problem arises in the above-described technology even in cases when a device other than a PLL is adopted.
In addition, with the technology disclosed in Patent Literature 2 and Patent Literature 3, when the target frequency is changed, for example the voltage impressed on the VCO must be controlled each 1,000 counts and time is needed for the frequency of the clock signal generated by the VCO to match the target frequency (appropriately including approximate matches that take errors and the like into consideration; the same also being true with the present invention). For example, if the voltage impressed on the VCO is changed in 1,000 steps, if the frequency of the clock signal does not match the target frequency, there are cases where dozens of seconds are needed in order for the frequency of the clock signal to match the target frequency. This kind of problem arises in the above-described technology even when other than PLL and VCO are adopted.